Ran He, Ph.D., 3D IC & Advanced Packaging

Project Researcher, Department of Precision Engineering, The University of Tokyo

Ɍesearch interests: low-temperature wafer bonding (especially surface activated bonding methods and Cu/adhesive and Cu/oxide hybrid bonding techniques), semiconductor advanced packaging, 3D interconnects, and 3D IC technology.


Senior Engineer, Huawei Technologies Co., Ltd., Apr. 2018 — Present

Project Researcher, The University of Tokyo, Oct. 2015 — Mar. 2018

Department of Precision Engineering, School of Engineering, The University of Tokyo, Tokyo, Japan

Research Subjects:

  1. Surface Activated Bonding (SAB) Methods
  • Combined SAB. Si-containing Ar beam and prebonding attach-detach procedure was combined to reduce bonding temperature of dielectric (like SiO2 and SiNx) and Cu films to sub-200 °C.

  • Modified SAB using Si nano-intermediate layer. Using in situ Ar beam bombardment and Si nano-intermediate layer deposition, bonding of semiconductors and dielectric can be obtained at room temperature.

  • Sequential Plasma Activation Bonding. Various combinations of O2 plasma, N2 plasma, and N radical activations are investigated for pre-bonding surface activation to improve the bonding energy achieved after post-bonding annealing at sub-200 °C.

  • H-containing HCOOH vapor treatment for sub-200 °C metal bonding/sintering.

  1. Hydrophilic direct bonding (SiO2–SiO2, SiO2–SiNx, and glass–glass) at sub-200 °C

  2. Cu/SiO2 Hybrid Bonding at sub-200 °C for 3D IC

  3. Cu/Adhesive Hybrid Bonding at sub-200 °C for 2.5D/3D IC

Research Subjects: Combined surface activation approaches for

  1. Dielectric (SiO2-SiO2 and SiO2-SiNx) bonding and
  2. Cu/dielectric (SiO2, SiNx, polymer adheisve) hybrid bonding for 3D integration.


  1. Deep understanding and 5 years hands-on experience in low-temperature wafer bonding (room temperature to 200 °C) for semiconductor integration/advanced packaging/3D IC.
  2. 3 years hands-on experience in silicon wet chemical and reactive ion etching, metal film sputter deposition, wafer grinding/thinning, through-silicon via (TSV) formation and filling.
  3. Skilled in characterizations by using AFM, XPS, TEM, EDS, SAM, and bond strength measurements, etc.
  4. Fluent English and Chinese (Mandarin) in speaking and writing; good teamwork capability.


Ph.D., Oct. 2012 — May 2016, Univ. of Tokyo

Department of Precision Engineering, School of Engineering, The University of Tokyo, Tokyo, Japan

Supervisor: Tadamoto Suga

Thesis: Combined Surface Activation Approaches to Low-Temperature Wafer Bonding for 3D Integration.

  1. Development of new wafer surface activation methods for low-temperature (≤200 °C) dielectric (SiO2-SiO2 and SiO2-SiNx) and Cu/dielectric (Cu/adhesive and Cu/oxide) hybrid bonding,
  2. Chemical/mechanical/electrical/microstructure characterization of the bonding surface/interface, and
  3. Study of mechanisms of the surface activations and bonding.

Master, Sep. 2009 — Jul. 2012, IMECAS

Institute of Microelectronics, Chinese Academy of Sciences (CAS), Beijing, China

Supervisor: Daquan Yu

Research Subjects:

  1. Development of through-silicon vias (TSVs) filling process by using Cu-cored solder ball, in charge of the thermal-mechanical simulation, and process planning and running (photolithography, reactive ion etching, Ti/Cu sputtering deposition, TSV fill, etc.),
  2. Si-based 3D PN junction capacitor for passive integration on Si interposer, assisting the process optimizing and testing of the capacitor.

Bachelor, Sep. 2005 — Jul. 2009, HUST

Department of Electronic Science and Technology, Huazhong University of Science and Technology (HUST), Wuhan, China

One year of experience with Barium Strontium Titanate (Ba1-xSrxTiO3, BST) ferroelectric ceramics and SnO2 gas sensor research and development.


  1. Award for Outstanding Student Presentation, 2014 ECS and SMEQ Joint International Meeting, P6: Semiconductor Wafer Bonding 13: Science, Technology, and Applications. Cancun, Mexico. October 5-9, 2014.
  2. Japanese Government (Monbukagakusho) Scholarship for Ph.D. study, Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan, 2012-2015.
  3. Outstanding Paper Award, 2011 12th International Conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), Shanghai, China. August 8-11, 2011.

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